Symbolic Analysis of Circuit Reliability

Due to shrinking feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susceptible to soft errors than memories. To estimate the susceptibility to errors in combinational logic, we propose the use of Binary Decision Diagrams (BDDs) and Algebraic Decision Diagrams (ADDs) for unified symbolic analysis of circuit reliability. present a framework that uses BDDs and ADDs and enables analysis of combinational circuits reliability from different aspects: output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less then O. 1%, for large circuits and small (20% of clock period) glitches, up about 30% for very small circuits and large enough (50% of clock period) glitches.